GENERAL DESCRIPTION

The ML6510 (Super PACMan?) is a Programmable Adaptive Clock Manager which offers an ideal solution for managing high speed synchronous clock distribution in next generation, high speed personal computer and workstation system designs. It provides eight channels of deskew buffers that adaptively compensate for clock skew using only a single trace. The input clock can be either TTL or PECL, selected by a bit in the control register. Frequency multiplication or division is possible using the M&N divider ratio, within the maximum frequency limit. 0.5X, 1X, 2X and 4X clocks can be easily realized.

FEATURES

■ Input clocks can be either TTL or PECL with low input to output clock phase error

■ 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip)

■ Controlled edge rate TTL-compatible CMOS clock outputs capable of driving 40? PCB traces

■ 10 to 80MHz (6510-80) or 10 to 130MHz (6510-130) input and output clock frequency range

■ Less than 500ps skew between inputs at the device loads

■ Small-swing reference clock outputs for minimizing part-to-part skew

■ Frequency multiplication or division is possible using the M&N divider ratio

■ Lock output indicates PLL and deskew buffer lock

■ Test mode operation allows PLL and deskew buffer bypass for board debug

■ Supports industry standard processors like Pentium,? Mips, SPARC,? PowerPC,? Alpha,? etc.