MKE17Z512VLH9中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

?This document provides electrical specifications for Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Data Sheet

?For functional characteristics and the programming model, see Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Reference Manual.

2.1

System features

The following sections describe the high-level system features.

2.1.1

ARM Cortex-M0+ core

The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability. The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward compatible with other Cortex-M profile processors.

2.1.2

NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority levels for interrupts. In the NVIC, each source in the IPR registers contains 2 bits. It also differs in number of interrupt sources and supports 32 interrupt vectors.

The Cortex-M family uses a number of methods to improve interrupt latency to up to 15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and VLPW modes.

2.1.3

AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Partial Stop, Stop and VLPS modes.

Wake-up sources for this SoC are listed as below:

2.1.4

Memory

This device has the following features:

?Up to 512 KB of embedded program flash memory, dual-bank flash supporting flash SWAP feature.

?Up to 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.

2.1.5

Reset and boot

The following table lists all the reset sources supported by this device.