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MK2049-35SI中文資料ICST數(shù)據(jù)手冊PDF規(guī)格書

MK2049-35SI
廠商型號

MK2049-35SI

功能描述

3.3 V Communications Clock PLL

文件大小

125.68 Kbytes

頁面數(shù)量

10

生產(chǎn)廠商 Integrated Circuit Systems
企業(yè)簡稱

ICST

中文名稱

Integrated Circuit Systems官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2025-1-28 14:30:00

MK2049-35SI規(guī)格書詳情

Description

The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems.

Features

? Packaged in 20 pin SOIC

? 3.3 V ±5 operation

? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E

? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz

? Locks to 8 kHz ±100 ppm (External mode)

? Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs

? Exact internal ratios enable zero ppm error

? Output clock rates include T1, E1, T3, E3, and OC3 submultiples

? See the MK2049-01, -02, and -03 for more selections at VDD = 5 V, and the MK2049-34 for more selections at 3.3 V

產(chǎn)品屬性

  • 型號:

    MK2049-35SI

  • 制造商:

    Integrated Device Technology Inc

  • 功能描述:

    49.152 MHz, OTHER CLOCK GENERATOR, PDSO20

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
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