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MH16S64PHB-7中文資料三菱電機(jī)數(shù)據(jù)手冊PDF規(guī)格書
| 廠商型號(hào) |
MH16S64PHB-7 |
| 功能描述 | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM |
| 文件大小 |
589.92 Kbytes |
| 頁面數(shù)量 |
55 頁 |
| 生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
| 企業(yè)簡稱 |
Mitsubishi【三菱電機(jī)】 |
| 中文名稱 | 三菱電機(jī)半導(dǎo)體（Mitsubishi Electric Semiconductor）官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊 | |
| 更新時(shí)間 | 2024-11-19 9:29:00 |
MH16S64PHB-7規(guī)格書詳情
DESCRIPTION
The MH16S64PHB is 16777216 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 16Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.
This is a socket type - memory modules, suitable for easy interchange or addition of modules.
FEATURES
? Utilizes industry standard 16M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP
? 168-pin (84-pin dual in-line package)
? single 3.3V±0.3V power supply
? Clock frequency 100MHz
? Fully synchronous operation referenced to clock rising edge
? 4 bank operation controlled by BA0,1(Bank Address)
? /CAS latency- 2/3(programmable)
? Burst length- 1/2/4/8/Full Page(programmable)
? Burst type- sequential / interleave(programmable)
? Column access - random
? Auto precharge / All bank precharge controlled by A10
? Auto refresh and Self refresh
? LVTTL Interface
? 4096 refresh cycle /64ms
? Discrete IC and module design conform to PC100 specification.
(module Spec. Rev. 1.0 and SPD 1.2A(-7,-8), SPD 1.0(-10))
APPLICATION
PC main memory
