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MH16D72AKLB-10中文資料三菱電機(jī)數(shù)據(jù)手冊PDF規(guī)格書
廠商型號(hào) |
MH16D72AKLB-10 |
功能描述 | 1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
文件大小 |
348.18 Kbytes |
頁面數(shù)量 |
39 頁 |
生產(chǎn)廠商 | Mitsubishi Electric Semiconductor |
企業(yè)簡稱 |
Mitsubishi【三菱電機(jī)】 |
中文名稱 | 三菱電機(jī)半導(dǎo)體(Mitsubishi Electric Semiconductor)官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊 | |
更新時(shí)間 | 2024-11-19 16:20:00 |
MH16D72AKLB-10規(guī)格書詳情
DESCRIPTION
The MH16D72AKLB is 16777216 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 9 industry standard 16M x 8 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.
FEATURES
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memoryunit for PC, PCserver
產(chǎn)品屬性
- 型號(hào):
MH16D72AKLB-10
- 制造商:
MITSUBISHI
- 制造商全稱:
Mitsubishi Electric Semiconductor
- 功能描述:
1,207.959,552-BIT(16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module