[MEMPHIS]

GENERAL DESCRIPTION

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MEM4X16E43VTW. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 column-address bits (A0-A9) on the MEM4X16E43VTW version. In addition, the byte and word accesses are supported via the two CAS# pins (CASL# and CASH#).

FEATURES

? Single +3.3V ±0.3V power supply

? Industry-standard x16 pinout, timing, functions, and package

? 12 row, 10 column addresses (4)

13 row, 9 column addresses (8)

? High-performance CMOS silicon-gate process

? All inputs, outputs and clocks are LVTTL-compatible

? Extended Data-Out (EDO) PAGE MODE access

? 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms

? Self refresh for low-power data retention