MC74LVX257DR2集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書(shū)PDF中文資料

MC74LVX257DR2屬于集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器。由安森美半導(dǎo)體公司制造生產(chǎn)的MC74LVX257DR2信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開(kāi)關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類(lèi)似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無(wú)窮變化量。

Quad 2-Channel Multiplexer with 3-State Outputs

The MC74LVX257 is an advanced high speed CMOS quad 2?channel multiplexer fabricated with silicon gate CMOS technology.

It consists of four 2?input digital multiplexers with common select (S) and enable (OE) inputs. When (OE) is held High, selection of data is inhibited and all the outputs go Low.

The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs.

The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.

Features

? High Speed: tPD = 4.5 ns (Typ) at VCC = 3.3 V

? Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C

? High Noise Immunity: VNIH = VNIL = 28 VCC

? Power Down Protection Provided on Inputs

? Balanced Propagation Delays

? Designed for 2.0 V to 5.5 V Operating Range

? Low Noise: VOLP = 0.8 V (Max)

? Pin and Function Compatible with Other Standard Logic Families

? Latchup Performance Exceeds 300 mA

? Chip Complexity: FETs = 100; Equivalent Gates = 25

? ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

? Pb?Free Packages are Available*