Dual D?Type Positive Edge?Triggered Flip?Flop

The MC74AC74/74ACT74 is a dual D?type flip?flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to SD(Set) sets Q to HIGH level

LOW input to CD(Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features

?Outputs Source/Sink 24 mA

?′ACT74 Has TTL Compatible Inputs

?Pb?Free Packages are Available

MC74ACT74DR2屬于集成電路（IC） > 觸發(fā)器。安森美半導(dǎo)體公司制造生產(chǎn)的MC74ACT74DR2觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。