MAX98089EWY+T集成電路（IC）的編解碼器規(guī)格書PDF中文資料

MAX98089EWY+T屬于集成電路（IC）的編解碼器。由亞德諾半導體技術有限公司制造生產(chǎn)的MAX98089EWY+T編解碼器編解碼器是用于通過壓縮和解壓縮來轉(zhuǎn)換數(shù)據(jù)的半導體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲空間。某些編解碼器提供高達 32 位的分辨率，并且分別提供多達 6 個或 8 個模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。

Features

● 5.6mW Power Comsumption (DAC to HP at 97dB DR)

● 101dB DR Stereo DAC (8kHz < fS < 96kHz)

● 93dB DR Stereo ADC (8kHz < fS < 96kHz)

● Stereo Low EMI Class D Amplifiers

1.7W/Channel (8Ω, VSPK_VDD = 5.0V)

2.9W/Channel (4Ω, VSPK_VDD = 5.0V)

● Efficient Class H Headphone Amplifier

● Differential Receiver Amplifier/Stereo Line Outputs

● 2 Stereo Single-Ended/Mono Differential Line Inputs

● 3 Differential Microphone Inputs

● FlexSound Technology

5-Band Parametric EQ

Automatic Level Control (ALC)

Excursion Limiter

Speaker Power Limiter

Speaker Distortion Limiter

Microphone Automatic Gain Control

and Noise Gate

● Dual I2S/PCM/TDM Digital Audio Interfaces

● Asynchronous Digital Mixing

● Supports Master Clock Frequencies from 10MHz to

60MHz

● RF Immune Analog Inputs and Outputs

● Extensive Click-and-Pop Reduction Circuitry

● Available in 63-Bump WLP Package (3.80mm x

3.30mm, 0.4mm Pitch) and 56-Pin TQFN Package

(7mm x 7mm x 0.75mm)