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M54HC595F1R中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

M54HC595F1R
廠商型號(hào)

M54HC595F1R

功能描述

8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE

文件大小

282.9 Kbytes

頁(yè)面數(shù)量

13 頁(yè)

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體(ST)集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-11-19 22:30:00

M54HC595F1R規(guī)格書詳情

DESCRIPTION

The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated in silicon C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.

■ HIGH SPEED

fMAX = 55 MHz (TYP.) AT VCC = 5 V

■ LOW POWER DISSIPATION

ICC = 4 μA (MAX.) AT TA = 25 °C

■ HIGH NOISE IMMUNITY

VNIH = VNIL = 28 VCC (MIN.)

■ OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS FOR QA TO QH

10 LSTTL LOADS FOR QH’

■ SYMMETRICAL OUTPUT IMPEDANCE

|IOH| = IOL = 6 mA (MIN.) FOR QA TO QH

|IOH| = IOL = 4 mA (MIN.) FOR QH’

■ BALANCED PROPAGATION DELAYS

tPLH = tPHL

■ WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

■ PIN AND FUNCTION COMPATIBLE

WITH LSTTL 54/74LS595

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