M1026集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

GENERAL DESCRIPTION

The M1025/26 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1025/26 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.

FEATURES

◆ Integrated SAW delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz)

◆ Output frequencies of 62.5 to 175 MHz (Specify VCSO output frequency at time of order)

◆ LVPECL clock output (CML and LVDS options available)

◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL

◆ Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin)

◆ AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure

◆ Acknowledge pin (REF_ACK pin) indicates the actively selected reference input

◆ Hitless Switching (HS) options with or without Phase Build-out (PBO) to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reselection

◆ Pin-selectable feedback and reference divider ratios

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package