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LMK04828SNKDREP集成電路(IC)的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料
廠商型號 |
LMK04828SNKDREP |
參數(shù)屬性 | LMK04828SNKDREP 包裝為卷帶(TR);類別為集成電路(IC)的時鐘發(fā)生器PLL頻率合成器;產(chǎn)品描述:LMK04828SNKDREP |
功能描述 | LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner |
絲印標識 | |
封裝外殼 | WQFN |
文件大小 |
1.76875 Mbytes |
頁面數(shù)量 |
102 頁 |
生產(chǎn)廠商 | Texas Instruments |
企業(yè)簡稱 |
TI【德州儀器】 |
中文名稱 | 美國德州儀器公司官網(wǎng) |
原廠標識 | |
數(shù)據(jù)手冊 | |
更新時間 | 2025-2-1 11:30:00 |
LMK04828SNKDREP規(guī)格書詳情
1 Features
1? EP Features
– Gold Bondwires
– Temperature Range: –55 to +105 °C
– Lead Finish SnPb
? Maximum Distribution Frequency: 3.2 GHz
? JESD204B Support
? Ultra-Low RMS Jitter
– 88-fs RMS Jitter (12 kHz to 20 MHz)
– 91-fs RMS Jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
? Up to 14 Differential Device Clocks From PLL2
– Up to 7 SYSREF Clocks
– Maximum Clock Output Frequency 3.2 GHz
– LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs From PLL2
? Up to 1 Buffered VCXO/Crystal Output From PLL1
– LVPECL, LVDS, 2xLVCMOS Programmable
? Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
? Dual Loop PLLatinum? PLL Architecture
? PLL1
– Up to 3 Redundant Input Clocks
– Automatic and Manual Switchover Modes
– Hitless Switching and LOS
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode When Input Clocks are Lost
? PLL2
– Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-Doubler
– Two Integrated Low-Noise VCOs
? 50 Duty Cycle Output Divides, 1 to 32
(Even and Odd)
? Precision Digital Delay, Dynamically Adjustable
? 25-ps Step Analog Delay
? 3.15-V to 3.45-V Operation
? Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8
mm)
2 Applications
? Wireless Infrastructure
? Data Converter Clocking
? Networking, SONET/SDH, DSLAM
? Medical / Video / Military / Aerospace
? Test and Measurement
3 Description
The LMK04828-EP device is the industry's highest
performance clock conditioner with JESD204B
support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as highperformance
outputs for traditional clocking systems.
The high performance combined with features like the
ability to trade off between power or performance,
dual VCOs, dynamic digital delay, holdover, and
glitchless analog delay make the LMK04828-EP ideal
for providing flexible high-performance clocking trees.
產(chǎn)品屬性
- 產(chǎn)品編號:
LMK04828SNKDREP
- 制造商:
Texas Instruments
- 類別:
集成電路(IC) > 時鐘發(fā)生器,PLL,頻率合成器
- 包裝:
卷帶(TR)
- 描述:
LMK04828SNKDREP
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
TI(德州儀器) |
22+ |
WQFN-64 |
30000 |
只做原裝 |
詢價 | ||
TI(德州儀器) |
23+ |
QFN64EP(9x9) |
2886 |
原裝現(xiàn)貨,免費供樣,技術支持,原廠對接 |
詢價 | ||
TI/德州儀器 |
23+ |
13000 |
原廠授權一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種 |
詢價 | |||
TI |
三年內(nèi) |
1983 |
只做原裝正品 |
詢價 | |||
TI(德州儀器) |
2117+ |
- |
315000 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價 | ||
TI |
24+ |
- |
18948 |
專注TI原裝正品代理分銷,認準水星電子 |
詢價 | ||
TI/德州儀器 |
21+ |
WQFN64 |
13880 |
公司只售原裝,支持實單 |
詢價 | ||
TI |
22 |
WQFN |
10000 |
3月31原裝,微信報價 |
詢價 | ||
Texas Instruments |
24+ |
- |
56200 |
一級代理/放心采購 |
詢價 | ||
TI/德州儀器 |
23+ |
WQFN64 |
9990 |
只有原裝 |
詢價 |