LM3S101中文資料etc未分類制造商數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

[Luminary Micro, Inc.]

Architectural Overview

The Luminary Micro Stellaris? family of microcontrollers—the first ARM? Cortex?-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

Product Features

The LM3S101 microcontroller includes the following product features:

■ 32-Bit RISC Performance

– 32-bit ARM? Cortex?-M3 v7M architecture optimized for small-footprint embedded applications

– Thumb?-compatible Thumb-2-only instruction set processor core for high code density

– 20-MHz operation

– Hardware-division and single-cycle-multiplication

– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

– 14 interrupts with eight priority levels

– Unaligned data access, enabling data to be efficiently packed into memory

– Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control

■ Internal Memory

– 8 KB single-cycle flash

? User-managed flash block protection on a 2-KB block basis

? User-managed flash data programming

? User-defined and managed flash-protection block

– 2 KB single-cycle SRAM

■ General-Purpose Timers

– Two timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers

– 32-bit Timer modes:

? Programmable one-shot timer

? Programmable periodic timer

? Real-Time Clock when using an external 32-KHz clock as the input

? User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug

– 16-bit Timer modes:

? General-purpose timer function with an 8-bit prescaler

? Programmable one-shot timer

? Programmable periodic timer

? User-enabled stalling when the controller asserts CPU Halt flag during debug

– 16-bit Input Capture modes:

? Input edge count capture

? Input edge time capture

– 16-bit PWM mode:

? Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– ARM PrimeCell?-compliant peripheral and cell identification registers

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ Synchronous Serial Interface (SSI)

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE?, or Texas Instruments synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

■ UART

– Fully programmable 16C550-type UART

– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading

– Programmable baud-rate generator with fractional divider

– Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface

– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4 and 7/8

– Standard asynchronous communication bits for start, stop and parity

– False start bit detection

– Line-break generation and detection

■ Analog Comparators

– Two independent integrated analog comparators

– Configurable for output to drive an output pin or generate an interrupt

– Compare external pin input to external pin input or to internal programmable voltage reference

■ GPIOs

– 2 to 18 GPIOs, depending on configuration

– Programmable interrupt generation as either edge-triggered or level-sensitive

– Bit masking in both read and write operations through address lines

– Programmable control for GPIO pad configuration:

? Weak pull-up or pull-down resistors

? 2-mA, 4-mA, and 8-mA pad drive

? Slew rate control for the 8-mA drive

? Open drain enables

? Digital input enables

■ Power

– On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user adjustable from 2.25 V to 2.75 V

– Low-power options on controller: Sleep and Deep-sleep modes

– Low-power options for peripherals: software controls shutdown of individual peripherals

– User-enabled LDO unregulated voltage detection and automatic reset

– 3.3-V supply brownout detection and reporting via interrupt or reset

■ Flexible Reset Sources

– Power-on reset (POR)

– Reset pin assertion

– Brown-out (BOR) detector alerts to system power drops

– Software reset

– Watchdog timer reset

– Internal linear drop-out (LDO) regulator output goes unregulated

■ Additional Features

– Six reset sources

– Programmable clock source control

– Clock gating to individual peripherals for power savings

– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller

– Debug access via JTAG and Serial Wire interfaces

– Full JTAG boundary scan

■ Package

– 28-pin RoHS-compliant SOIC

– Commercial and industrial operating temperatures

Target Applications

■ Factory automation and control

■ Industrial control power devices

■ Building and home automation