LH543611中文資料夏普微數(shù)據(jù)手冊(cè)PDF規(guī)格書
廠商型號(hào) |
LH543611 |
功能描述 | 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO |
文件大小 |
475.96 Kbytes |
頁(yè)面數(shù)量 |
57 頁(yè) |
生產(chǎn)廠商 | Sharp Microelectronics of the Americas (SMA) |
企業(yè)簡(jiǎn)稱 |
SHARP【夏普微】 |
中文名稱 | 美國(guó)夏普微電子公司(SMA)官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-12-28 10:44:00 |
LH543611規(guī)格書詳情
FUNCTIONAL DESCRIPTION
The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and LH543621 are ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced.
FEATURES
? Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper
? Expanded Control Register that is Fully Readable as well as Writeable
? Fast Cycle Times: 18/20/25/30/35 ns
? Improved Input Setup and Flag Out Timing
? Two 512 × 36-bit FIFO Buffers (LH543611) or Two 1024 × 36-bit FIFO Buffers (LH543621)
? Full 36-bit Word Width
? Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Resetting the BiFIFO
? Programmable Byte-Order Reversal – ‘Big-Endian ? Little-Endian Conversion’
? Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B
? ‘Synchronous’ Enable-Plus-Clock Control at Both Ports
? R/W, Enable, Request, and Address Control Inputs are Sampled on the Rising Clock Edge
? Synchronous Request/Acknowledge ‘Handshake’ Capability; Use is Optional
? Device Comes Up Into a Known Default State at Reset; Programming is Allowed, but is not Required
? Asynchronous Output Enables
? Five Status Flags per Port: Full, Almost-Full, Half-Full, Almost-Empty, and Empty
? All Flags are Independently Programmable for Either Synchronous or Asynchronous Operation
? Almost-Full Flag and Almost-Empty Flag Have Programmable Offsets
? Mailbox Registers with Synchronized Flags
? Data-Bypass Function
? Data-Retransmit Function
? Automatic Byte Parity Checking with Programmable Parity Flag Latch
? Programmable Byte Parity Generation
? Programmable Byte, Half-Word, or Full-Word Oriented Parity Operations
? 8 mA-IOL High-Drive Three-State Outputs with Built-In Series Resistor
? TTL/CMOS-Compatible I/O
? Space-Saving PQFP and TQFP Packages
產(chǎn)品屬性
- 型號(hào):
LH543611
- 制造商:
SHARP
- 制造商全稱:
Sharp Electrionic Components
- 功能描述:
512 x 36 x 2/1024 x 36 x 2 Synchronous Bidirectional FIFO
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
SHARP |
24+ |
DIP-28 |
4650 |
詢價(jià) | |||
原廠 |
2023+ |
TSOP |
50000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
SHARP |
23+ |
DIP |
9526 |
詢價(jià) | |||
SHARP/夏普 |
18+ |
DIP28 |
12500 |
全新原裝正品,本司專業(yè)配單,大單小單都配 |
詢價(jià) | ||
SHARP |
2016+ |
DIP |
6523 |
只做原裝正品現(xiàn)貨!或訂貨! |
詢價(jià) | ||
TI |
TSSOP24 |
68900 |
原包原標(biāo)簽100%進(jìn)口原裝常備現(xiàn)貨! |
詢價(jià) | |||
SHRP |
22+ |
QFP |
2000 |
原裝正品現(xiàn)貨 |
詢價(jià) | ||
SHARP |
22+ |
PLCC |
680 |
原裝現(xiàn)貨熱賣中,提供一站式真芯服務(wù) |
詢價(jià) | ||
LH5464 |
300 |
300 |
詢價(jià) | ||||
TI |
24+ |
TSOP24 |
557 |
詢價(jià) |