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LH543611中文資料夏普微數(shù)據(jù)手冊PDF規(guī)格書

LH543611
廠商型號

LH543611

功能描述

512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO

文件大小

475.96 Kbytes

頁面數(shù)量

57

生產(chǎn)廠商 Sharp Microelectronics of the Americas (SMA)
企業(yè)簡稱

SHARP夏普微

中文名稱

美國夏普微電子公司(SMA)官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2025-2-1 16:42:00

LH543611規(guī)格書詳情

FUNCTIONAL DESCRIPTION

The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits. The LH543611 and LH543621 are ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced.

FEATURES

? Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper

? Expanded Control Register that is Fully Readable as well as Writeable

? Fast Cycle Times: 18/20/25/30/35 ns

? Improved Input Setup and Flag Out Timing

? Two 512 × 36-bit FIFO Buffers (LH543611) or Two 1024 × 36-bit FIFO Buffers (LH543621)

? Full 36-bit Word Width

? Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Resetting the BiFIFO

? Programmable Byte-Order Reversal – ‘Big-Endian ? Little-Endian Conversion’

? Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B

? ‘Synchronous’ Enable-Plus-Clock Control at Both Ports

? R/W, Enable, Request, and Address Control Inputs are Sampled on the Rising Clock Edge

? Synchronous Request/Acknowledge ‘Handshake’ Capability; Use is Optional

? Device Comes Up Into a Known Default State at Reset; Programming is Allowed, but is not Required

? Asynchronous Output Enables

? Five Status Flags per Port: Full, Almost-Full, Half-Full, Almost-Empty, and Empty

? All Flags are Independently Programmable for Either Synchronous or Asynchronous Operation

? Almost-Full Flag and Almost-Empty Flag Have Programmable Offsets

? Mailbox Registers with Synchronized Flags

? Data-Bypass Function

? Data-Retransmit Function

? Automatic Byte Parity Checking with Programmable Parity Flag Latch

? Programmable Byte Parity Generation

? Programmable Byte, Half-Word, or Full-Word Oriented Parity Operations

? 8 mA-IOL High-Drive Three-State Outputs with Built-In Series Resistor

? TTL/CMOS-Compatible I/O

? Space-Saving PQFP and TQFP Packages

產(chǎn)品屬性

  • 型號:

    LH543611

  • 制造商:

    SHARP

  • 制造商全稱:

    Sharp Electrionic Components

  • 功能描述:

    512 x 36 x 2/1024 x 36 x 2 Synchronous Bidirectional FIFO

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