KAD5612P-25Q72集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

廠商型號	KAD5612P-25Q72
參數(shù)屬性	KAD5612P-25Q72 封裝/外殼為72-VFQFN 裸露焊盤；包裝為管件；類別為集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）；產(chǎn)品描述：IC ADC 12BIT SAR 72QFN
功能描述	Dual 12-Bit, 250/210/170/125MSPS A/D Converter
封裝外殼	72-VFQFN 裸露焊盤
文件大小	595.28 Kbytes
頁面數(shù)量	29 頁
生產(chǎn)廠商	Intersil Corporation
企業(yè)簡稱	INTERSIL
中文名稱	Intersil Corporation官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-8-1 10:19:00
人工找貨	KAD5612P-25Q72價格和庫存，歡迎聯(lián)系客服免費人工找貨

The KAD5612P is a family of low-power, high-performance,

dual-channel 12-bit, analog-to-digital converters. Designed

with FemtoCharge? technology on a standard CMOS

process, the family supports sampling rates of up to

250MSPS. The KAD5612P-25 is the fastest member of this

pin-compatible family, which also features sample rates of

210MSPS (KAD5612P-21), 170MSPS (KAD5612P-17) and

125MSPS (KAD5612P-12).

A serial peripheral interface (SPI) port allows for extensive

configurability, as well as fine control of gain, skew and offset

matching between the two converter cores.

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5612P is available in a 72-contact QFN

package with an exposed paddle. Performance is specified

over the full industrial temperature range (-40°C to +85°C).

特性 Features

? Programmable Gain, Offset and Skew Control

? 1.3GHz Analog Input Bandwidth

? 60fs Clock Jitter

? Over-Range Indicator

? Selectable Clock Divider: ÷1, ÷2 or ÷4

? Clock Phase Selection

? Nap and Sleep Modes

? Two’s Complement, Gray Code or Binary Data Format

? DDR LVDS-Compatible or LVCMOS Outputs

? Programmable Built-in Test Patterns

? Single-Supply 1.8V Operation

? Pb-Free (RoHS Compliant)

Applications

? Power Amplifier Linearization

? Radar and Satellite Antenna Array Processing

? Broadband Communications

? High-Performance Data Acquisition

? Communications Test Equipment

? WiMAX and Microwave Receivers