首頁(yè)>ISPLSI1024EA-100LT100>規(guī)格書詳情

ISPLSI1024EA-100LT100中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

ISPLSI1024EA-100LT100
廠商型號(hào)

ISPLSI1024EA-100LT100

功能描述

In-System Programmable High Density PLD

文件大小

162.63 Kbytes

頁(yè)面數(shù)量

13 頁(yè)

生產(chǎn)廠商 Lattice Semiconductor
企業(yè)簡(jiǎn)稱

Lattice萊迪思

中文名稱

萊迪思半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-11 16:49:00

ISPLSI1024EA-100LT100規(guī)格書詳情

Description

The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP).

Features

? HIGH DENSITY PROGRAMMABLE LOGIC

— 4000 PLD Gates

— 48 I/O Pins, Two Dedicated Inputs

— 144 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

? NEW FEATURES

— 100 IEEE 1149.1 Boundary Scan Testable

— ispJTAG? In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User Selectable 3.3V or 5V I/O Supports

MixedVoltage Systems (VCCIO Pin)

— Open-Drain Output Option

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 200 MHz Maximum Operating Frequency

— tpd = 4.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

? IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-Market

and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

? OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

? ispDesignEXPERT? – LOGIC COMPILER

AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER?

— PC and UNIX Platforms

產(chǎn)品屬性

  • 型號(hào):

    ISPLSI1024EA-100LT100

  • 功能描述:

    CPLD - 復(fù)雜可編程邏輯器件

  • RoHS:

  • 制造商:

    Lattice

  • 存儲(chǔ)類型:

    EEPROM

  • 大電池?cái)?shù)量:

    128

  • 最大工作頻率:

    333 MHz

  • 延遲時(shí)間:

    2.7 ns

  • 可編程輸入/輸出端數(shù)量:

    64

  • 工作電源電壓:

    3.3 V

  • 最大工作溫度:

    + 90 C

  • 最小工作溫度:

    0 C

  • 封裝/箱體:

    TQFP-100

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
Lattice
22+23+
TQFP100
18168
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
詢價(jià)
Lattice
TQFP100
68900
原包原標(biāo)簽100%進(jìn)口原裝常備現(xiàn)貨!
詢價(jià)
LATTICE/萊迪斯
2022
TQFP100
80000
原裝現(xiàn)貨,OEM渠道,歡迎咨詢
詢價(jià)
Lattice
17+
6200
100%原裝正品現(xiàn)貨
詢價(jià)
LATTICE
2020+
QFP
80000
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增
詢價(jià)
LATTICE
24+
FPGA
5268
原裝現(xiàn)貨
詢價(jià)
Lattice
16+
TQFP
2500
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢(shì)!
詢價(jià)
Lattice
23+
TQFP100
7000
詢價(jià)
LATTICE SEMICONDUCTOR
2022+
原廠原包裝
8600
全新原裝 支持表配單 中國(guó)著名電子元器件獨(dú)立分銷
詢價(jià)
Lattice
23+
TQFP100
8000
只做原裝現(xiàn)貨
詢價(jià)