IDTCV125PA中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This chip has four PLLs inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device also implements Band-gap referenced IREFto reduce the impact of VDDvariation on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own Spread Spectrum selection.

FEATURES:

? Power management control suitable for notebook applications

? One high precision PLL for CPU, SSC and N programming

? One high precision PLL for SRC/PCI, supports 100MHz output frequency, SSC and N programming

? One high precision PLL for LVDS. Supports 100/96MHz output frequency, SSC programming

? One high precision PLL for 96MHz/48MHz

? Band-gap circuit for differential outputs

? Support spread spectrum modulation, –0.5 down spread and others

? Support SMBus block read/write, index read/write

? Selectable output strength for REF

? Allows for CPU frequency to change to a slower frequency to conserve power when an application is less execution intensive

? Smooth transition for N programming

? Available in TSSOP package