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IDT72T20118L10BB集成電路（IC）的FIFO存儲器規(guī)格書PDF中文資料
| 廠商型號 |
IDT72T20118L10BB |
| 參數(shù)屬性 | IDT72T20118L10BB 封裝/外殼為208-BGA；包裝為管件；類別為集成電路（IC）的FIFO存儲器；產(chǎn)品描述：IC FIFO 65536X20 10NS 208BGA |
| 功能描述 | 2.5 VOLT HIGH-SPEED TeraSync??DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 封裝外殼 | 208-BGA |
| 文件大小 |
481.75 Kbytes |
| 頁面數(shù)量 |
51 頁 |
| 生產(chǎn)廠商 | Integrated Device Technology, Inc. |
| 企業(yè)簡稱 |
IDT |
| 中文名稱 | Integrated Device Technology, Inc.官網(wǎng) |
| 原廠標識 |  |
| 數(shù)據(jù)手冊 | |
| 更新時間 | 2025-1-17 15:02:00 |
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DESCRIPTION:
The IDT72T2098/72T20108/72T20118/72T20128 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability to read and write data on both rising and falling edges of clock. The device has a flexible x20/x10 Bus-Matching mode and the option to select Single or Double Data clock rates for input and output ports.
FEATURES:
? Choose among the following memory organizations:
IDT72T2098 - 32,768 x 20/65,536 x 10
IDT72T20108 - 65,536 x 20/131,072 x 10
IDT72T20118 - 131,072 x 20/262,144 x 10
IDT72T20128 - 262,144 x 20/524,288 x 10
? Up to 250MHz Operation of Clocks
- 4ns read/write cycle time, 3.2ns access time
? Users selectable input port to output port data rates, 500Mb/s Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
? User selectable HSTL or LVTTL I/Os
? Read Enable & Read Clock Echo outputs aid high speed operation
? 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
? 3.3V Input tolerant
? Mark & Retransmit, resets read pointer to user marked position
? Write Chip Select (WCS) input enables/disables Write Operations
? Read Chip Select (RCS) synchronous to RCLK
? Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets
? Dedicated serial clock input for serial programming of flag offsets
? User selectable input and output port bus sizing
-x20 in to x20 out
-x20 in to x10 out
-x10 in to x20 out
-x10 in to x10 out
? Auto power down minimizes standby power consumption
? Master Reset clears entire FIFO
? Partial Reset clears data, but retains programmable settings
? Empty and Full flags signal FIFO status
? Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
? Output enable puts data outputs into High-Impedance state
? JTAG port, provided for Boundary Scan function
? 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
? Easily expandable in depth and width
? Independent Read and Write Clocks (permit reading and writing simultaneously)
? High-performance submicron CMOS technology
? Industrial temperature range (-40°C to +85°C) is available
產(chǎn)品屬性
- 產(chǎn)品編號：
IDT72T20118L10BB
- 制造商：
Renesas Electronics America Inc
- 類別：
集成電路（IC） > FIFO 存儲器
- 系列：
72T
- 包裝：
管件
- 存儲容量：
2.5M（128K x 20）（256K x 10）
- 功能：
同步
- 數(shù)據(jù)速率：
100MHz
- 訪問時間：
4.5ns
- 電流 - 供電（最大值）：
60mA
- 總線方向：
單向
- 擴充類型：
深度，寬度
- 可編程標志支持：
是
- 中繼能力：
是
- FWFT 支持：
是
- 工作溫度：
0°C ~ 70°C
- 安裝類型：
表面貼裝型
- 封裝/外殼：
208-BGA
- 供應商器件封裝：
208-PBGA（17x17）
- 描述：
IC FIFO 65536X20 10NS 208BGA
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
IDT |
22+ |
208PBGA |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價 | ||
IDT |
2022+ |
原廠原包裝 |
38550 |
全新原裝 支持表配單 中國著名電子元器件獨立分銷 |
詢價 | ||
IDT, Integrated Device Techno |
23+ |
208-PBGA17x17 |
7300 |
專注配單,只做原裝進口現(xiàn)貨 |
詢價 | ||
IDT, Integrated Device Techno |
23+ |
208-PBGA17x17 |
7300 |
專注配單,只做原裝進口現(xiàn)貨 |
詢價 | ||
Renesas Electronics America In |
24+ |
208-BGA |
9350 |
獨立分銷商 公司只做原裝 誠心經(jīng)營 免費試樣正品保證 |
詢價 | ||
IDT |
21+ |
208PBGA |
13880 |
公司只售原裝,支持實單 |
詢價 | ||
IDT, Integrated Device Technol |
24+ |
208-PBGA(17x17) |
53200 |
一級代理/放心采購 |
詢價 | ||
IDT |
23+ |
NA |
19960 |
只做進口原裝,終端工廠免費送樣 |
詢價 | ||
IDT |
23+ |
208PBGA |
9000 |
原裝正品，支持實單 |
詢價 | ||
IDT |
20+ |
BGA-208 |
1001 |
就找我吧!--邀您體驗愉快問購元件! |
詢價 |
