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IDT71V35781S200BQ中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書
| 廠商型號 |
IDT71V35781S200BQ |
| 功能描述 | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| 文件大小 |
282.83 Kbytes |
| 頁面數(shù)量 |
22 頁 |
| 生產(chǎn)廠商 | Integrated Device Technology, Inc. |
| 企業(yè)簡稱 |
IDT |
| 中文名稱 | Integrated Device Technology, Inc.官網(wǎng) |
| 原廠標(biāo)識 |  |
| 數(shù)據(jù)手冊 | |
| 更新時間 | 2024-11-20 16:53:00 |
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IDT71V35781S200BQ規(guī)格書詳情
Description
The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.
Features
◆128K x 36, 256K x 18 memory configurations
◆Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
◆LBOinput selects interleaved or linear burst mode
◆Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
◆3.3V core power supply
◆Power down controlled by ZZ input
◆3.3V I/O
◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant)
◆Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array
