首頁 >ICY7C1373D-100BGXI>規(guī)格書列表
| 零件編號(hào) | 下載&訂購 | 功能描述 | 制造商&上傳企業(yè) | LOGO |
|---|---|---|---|---|
ICY7C1373D-100BGXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | |
18-Mbit(512K?36/1M?18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress | ||
18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo | CypressCypressSemiconductor 賽普拉斯賽普拉斯半導(dǎo)體公司 | Cypress |
詳細(xì)參數(shù)
- 型號(hào)：
ICY7C1373D-100BGXI
- 制造商：
CYPRESS
- 制造商全稱：
Cypress Semiconductor
- 功能描述：
18-Mbit(512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SONY |
23+ |
65480 |
詢價(jià) | ||||
XP |
20+ |
電源模塊 |
335 |
就找我吧!--邀您體驗(yàn)愉快問購元件! |
詢價(jià) | ||
XP Power |
2022+ |
原廠原包裝 |
6800 |
全新原裝 支持表配單 中國(guó)著名電子元器件獨(dú)立分銷 |
詢價(jià) | ||
XP Power |
24+ |
N/A |
12000 |
一級(jí)代理保證進(jìn)口原裝正品假一罰十價(jià)格合理 |
詢價(jià) | ||
24+ |
N/A |
53000 |
一級(jí)代理-主營(yíng)優(yōu)勢(shì)-實(shí)惠價(jià)格-不悔選擇 |
詢價(jià) | |||
XP POWER |
22+ |
DIP |
10000 |
詢價(jià) |
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