ICS8EN31AK中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

* Nine differential 3.3V LVPECL outputs

* Selectable differential CLK, nCLK or LVPECL clock inputs

* CLK, nCLK pair can accept the following differential input

levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

* PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

* Maximum output frequency: 500MHz

? Translates any single ended input signal (LVCMOS,

LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on

nCLK input

* Output skew: 40ps (maximum)

* Part-to-part skew: 350ps (maximum)

? Propagation delay: 1.9ns (maximum)

* 3.3V operating supply

* 0°C to 70°C ambient operatina temperature