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ICS853S9252I中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

ICS853S9252I
廠商型號

ICS853S9252I

功能描述

2.5V, 3.3V ECL/LVPECL Clock/Data Fanout Buffer

文件大小

695.13 Kbytes

頁面數(shù)量

22

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-11-17 14:30:00

ICS853S9252I規(guī)格書詳情

General Description

The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer

designed for high-speed, low phase-noise wireless infrastructure

applications. The device fanouts a differential input signal to two

ECL/LVPECL outputs. Optimized for low additive phase-noise,

sub-100ps output rise and fall times, low output skew and

high-frequencies, the ICS853S9252I is an effective solution for

high-performance clock and data distribution applications, for

instance driving the reference clock inputs of ADC/DAC circuits.

Internal input termination, a bias voltage output (VREF) for

AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN)

supports space-efficient board designs.

The ICS853S9252I operates from a full 2.5V or 3.3V power supply

and supports the industrial temperature range of -40°C to 85°C. The

extended temperature range also supports wireless infrastructure,

tele-communication and networking end equipment requirements.

Features

? 1:2 differential clock/data fanout buffer

? Clock frequency: 3GHz (maximum)

? Two differential 2.5V/3.3V ECL/LVPECL clock output

? Differential input accepts ECL/LVPECL, LVDS and CML levels

? Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)

? Propagation delay: 175ps (maximum), VCC = 3.3V

? Output rise/fall time: 135ps (maximum), VCC = 3.3V

? Internal input signal termination

? Supply voltage: 2.5V-5 to 3.3V+10

? Lead-free (RoHS 6) packaging

? -40°C to 85°C ambient operating temperature

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