ICS8523I中文資料華潤微電子數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ICS8523I is a low skew, high performance 1-to-4 Differential-to-HSTL fanout buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS8523I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8523I ideal for those applications demanding well defined performance and repeatability.

FEATURES

? 4 differential HSTL compatible outputs

? Selectable diffferential CLK, nCLK or LVPECL clock inputs

? CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL

? PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL

? Maximum output frequency: 650MHz

? Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input

? Output skew: 50ps (maximum)

? Part-to-part skew: 250ps (maximum)

? Propagation delay: 1.6ns (maximum)

? 3.3V core, 1.8V output operating supply

? Lead-Free package available

? -40°C to 85°C ambient operating temperature