ICS8521中文資料華潤微電子數(shù)據(jù)手冊(cè)PDF規(guī)格書

GENERAL DESCRIPTION

The ICS8521 is a low skew, 1-to-9 Differentialto-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

FEATURES

? 9 HSTL outputs

? Selectable differential CLK, nCLK or LVPECL clock inputs

? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL

? PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL

? Maximum output frequency: 500MHz

? Output skew: 50ps (maximum)

? Part-to-part skew: 250ps (maximum)

? Propagation delay: 1.8ns (maximum)

? VOH = 1.4V (maximum)

? 3.3V core, 1.8V output operating supply voltages

? 0°C to 70°C ambient operating temperature

? Industrial temperature information available upon request