IC61SP12836-5TQ中文資料ICSI數據手冊PDF規(guī)格書

DESCRIPTION

The ICSI IC61SP12832,IC61SP12836 are high-speed, low power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium?, 680X0?, and PowerPC? microprocessors. It is organized as 131,072 words by 32 bits, fabricated with ICSIs advanced CMOS technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

FEATURES

? Internal self-timed write cycle

? Individual Byte Write Control and Global Write

? Clock controlled, registered address, data and control

? Pentium? or linear burst sequence control using MODE input

? Three chip enables for simple depth expansion and address pipelining

? Common data inputs and data outputs

? 100-Pin TQFP (JEDEC LQFP) and 119-pin PBGA package

? Single +3.3V, +10, –5 power supply

? Power-down snooze mode