IC61LV256中文資料ICSI數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The ICSI IC61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ICSIs high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 600 μW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IC61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package.

FEATURES

? High-speed access times:

-- 8, 10, 12, 15 ns

? Automatic power-down when chip is deselected

? CMOS low power operation

-- 345 mW (max.) operating

-- 7 mW (max.) CMOS standby

? TTL compatible interface levels

? Single 3.3V power supply

? Fully static operation: no clock or refresh required

? Three-state outputs