HY57V561620B中文資料海力士數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The HY57V561620B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620B is organized as 4banks of 4,194,304x16.

HY57V561620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

FEATURES

? Single 3.3±0.3V power supply

? All device pins are compatible with LVTTL interface

? JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch

? All inputs and outputs referenced to positive edge of system clock

? Data mask function by UDQM, LDQM

? Internal four banks operation

? Auto refresh and self refresh

? 8192 refresh cycles / 64ms

? Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

? Programmable CAS Latency ; 2, 3 Clocks