HEF4060BT集成電路（IC）的計數(shù)器除法器規(guī)格書PDF中文資料

1. General description

The HEF4060B is a 14-stage ripple-carry counter/divider and oscillator with three oscillator

terminals (RS, REXT and CEXT), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an

overriding asynchronous master reset (MR). The oscillator configuration allows design of either

RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input

RS. In this case, keep the oscillator pins (REXT and CEXT) floating. The counter advances on the

HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs

LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use

of current limiting resistors to interface inputs to voltages in excess of VDD.

2. Features and benefits

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Complies with JEDEC standard JESD 13-B

? Tolerant of slow clock rise and fall times

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Standardized symmetrical output characteristics

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 ° C to +85 °C