HEF4015B集成電路（IC）的移位寄存器規(guī)格書(shū)PDF中文資料

1. General description

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each

shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs

(Q0 to Q3) and an overriding asynchronous master reset input (nMR). Information present on nD is

shifted to the first register position, and all the data in the register is shifted one position to the right

on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces Q0 to Q3 to

LOW, independent of nCP and nD. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VDD.

2. Features and benefits

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Tolerant of slow clock rise and fall times

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Standardized symmetrical output characteristics

? Complies with JEDEC standard JESD 13-B

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? Specified from -40 °C to +85 °C

3. Applications

? Serial-to-parallel converter

? Buffer stores

? General purpose register