首頁(yè)>HD74LVC125AFPEL>規(guī)格書詳情
HD74LVC125AFPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書
HD74LVC125AFPEL規(guī)格書詳情
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to be taken high to put the output into the high impedance condition, whereas the device requires the control input to be low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
? VCC = 2.0 V to 5.5 V
? All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
? All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
? Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
? Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
? High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HIT |
22+23+ |
5.2mm |
28026 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
NEC |
22+ |
TSSOP16 |
8000 |
原裝正品支持實(shí)單 |
詢價(jià) | ||
RENESAS |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
24+ |
SOP |
1361 |
詢價(jià) | ||||
RENESAS/瑞薩 |
22+ |
TSSOP14 |
9000 |
原裝正品 |
詢價(jià) | ||
RENESA |
2020+ |
SOP5.2 |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) | ||
NEC |
24+ |
TSSOP16 |
2000 |
詢價(jià) | |||
HITACHI |
1716+ |
TSSOP |
7500 |
只做原裝進(jìn)口,假一罰十 |
詢價(jià) | ||
23+ |
SO |
6500 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) | |||
23+ |
SO |
6500 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) |
