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HD74HC4024RPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

HD74HC4024RPEL
廠商型號(hào)

HD74HC4024RPEL

功能描述

7-stage Binary Counter

文件大小

91.59 Kbytes

頁(yè)面數(shù)量

7 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

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更新時(shí)間

2025-1-10 16:15:00

HD74HC4024RPEL規(guī)格書(shū)詳情

Description

The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.

Features

? High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC = 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)

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24+
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258
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RENESAS/瑞薩
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詢價(jià)