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HD74HC377RPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

HD74HC377RPEL
廠商型號(hào)

HD74HC377RPEL

功能描述

Octal D-type Flip-Flops (with Enable)

文件大小

99.38 Kbytes

頁面數(shù)量

7

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-9 12:03:00

HD74HC377RPEL規(guī)格書詳情

Description

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuitsare designed to prevent false clocking by transitions at the G input.

Features

? High Speed Operation: tpd= 13 ns typ (CL= 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC= 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC(static) = 4 μA max (Ta = 25°C)

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23+
SOP
7000
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詢價(jià)
HITACHI/日立
23+
SOP14
15000
一級(jí)代理原裝現(xiàn)貨
詢價(jià)
RENESAS/瑞薩
23+
DIP14
10000
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢(shì)訂貨,價(jià)格優(yōu)勢(shì)、品種
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21+
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6000
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詢價(jià)
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24+
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2987
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2023+
DIP
3000
進(jìn)口原裝現(xiàn)貨
詢價(jià)
HIT
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55963
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100500
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