HD74ALVCH16820中文資料日立數(shù)據(jù)手冊PDF規(guī)格書

Description

The flip flops of the HD74ALVCH16820 are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.

Features

? VCC = 2.3 V to 3.6 V

? Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

? Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

? High output current ±24 mA (@VCC = 3.0 V)

? Bus hold on data inputs eliminates the need for external pullup / pulldown resistors