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HD74AC112RPEL中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

HD74AC112RPEL
廠商型號

HD74AC112RPEL

功能描述

Dual JK Negative Edge-Triggered Flip-Flop

文件大小

240.9 Kbytes

頁面數(shù)量

10

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-11-16 22:59:00

HD74AC112RPEL規(guī)格書詳情

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop.

When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs

may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum

setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Features

? Outputs Source/Sink 24 mA

? HD74ACT112 has TTL-Compatible Inputs

? Ordering Information: Ex. HD74AC112

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