HD64F3048F16中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Overview

The H8/3048B Group is a series of microcontrollers (MCUs) that integrate system supporting

functions together with an H8/300H CPU core having an original Renesas Technology architecture. In addition, the H8/3048F-ONE is equipped with an on-chip emulator (E10T)*2.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit

(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial

communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory

access controller (DMAC), a refresh controller, and other facilities.

The H8/3048B Group has 128 kbytes of on-chip ROM and 4 kbytes of on-chip RAM. Seven MCU operating modes offer a choice of data bus width and address space size. The modes

(modes 1 to 7) include one single-chip mode and six expanded modes. In addition to mask ROM products, the H8/3048B Group includes F-ZTAT?* 1 version products with on-chip user-programmable flash memory. It enables users to respond quickly and flexibly to changing application specifications as well as to conditions when ramping up from initial to full

volume production. The on-chip emulator (E10T)*2 is capable of direct emulation of the

microcontroller when mounted in the user’s system, thereby making possible on-board program

debugging.