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HCS125中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

HCS125
廠商型號(hào)

HCS125

功能描述

Radiation Hardened Quad Buffer, Three-State

文件大小

93.82 Kbytes

頁(yè)面數(shù)量

9 頁(yè)

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡(jiǎn)稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-12-22 23:00:00

HCS125規(guī)格書詳情

Description

The Intersil HCS125MS is a Radiation Hardened quad three-state buffer, each having its own output enable input. A high level on the enable input puts the output in a high impedance state.

The HCS125MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS125MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features

? 3 Micron Radiation Hardened SOS CMOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset >1010 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range: -55°C to +125°C

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 30 of VCC Max

??? - VIH = 70 of VCC Min

? Input Current Levels Ii ≤ 5μA at VOL, VOH

產(chǎn)品屬性

  • 型號(hào):

    HCS125

  • 制造商:

    INTERSIL

  • 制造商全稱:

    Intersil Corporation

  • 功能描述:

    Radiation Hardened Quad Buffer, Three-State

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