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HC125中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

HC125
廠商型號(hào)

HC125

功能描述

QUAD BUS BUFFERS 3-STATE

文件大小

61.74 Kbytes

頁(yè)面數(shù)量

8 頁(yè)

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-12-22 23:00:00

HC125規(guī)格書詳情

DESCRIPTION

The 74VHC125 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 VCC (MIN.)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN)

■ BALANCED PROPAGATION DELAYS:

tPLH = tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: VOLP = 0.8V (MAX.)

產(chǎn)品屬性

  • 型號(hào):

    HC125

  • 制造商:

    FAIRCHILD

  • 制造商全稱:

    Fairchild Semiconductor

  • 功能描述:

    Quad Buffer with 3-STATE Outputs

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