GAL6002B-15LJ中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E2CMOS technology offers high speed (

Features

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— 15ns Maximum Propagation Delay

— 75MHz Maximum Frequency

— 6.5ns Maximum Clock to Output Delay

— TTL Compatible 16mA Outputs

— UltraMOS? Advanced CMOS Technology

? ACTIVE PULL-UPS ON ALL PINS

? LOW POWER CMOS

— 90mA Typical Icc

? E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

? UNPRECEDENTED FUNCTIONAL DENSITY

— 78 x 64 x 36 FPLA Architecture

— 10 Output Logic Macrocells

— 8 Buried Logic Macrocells

— 20 Input and I/O Logic Macrocells

? HIGH-LEVEL DESIGN FLEXIBILITY

— Asynchronous or Synchronous Clocking

— Separate State Register and Input Clock Pins

— Functional Superset of Existing 24-pin PAL?

and FPLA Devices

? APPLICATIONS INCLUDE:

— Sequencers

— State Machine Control

— Multiple PLD Device Integration