FW802中文資料agere數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
FW802規(guī)格書(shū)詳情
Description
The Agere Systems Inc. FW802A device provides the analog physical layer functions needed to implement a two-port node in a cable-based IEEE 1394-1995 and IEEE 1394a-2000 network.
Distinguishing Features
■ Compliant with IEEE Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1.
■ Low-power consumption during powerdown or microlow-power sleep mode.
■ Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
■ While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.
■ Does not require external filter capacitors for PLL.
■ Does not require a separate 5 V supply for 5 V link controller interoperability.
■ Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies.
■ Interoperable with 1394 link-layer controllers using 5 V supplies.
■ 1394a-2000 compliant common mode noise filter on incoming TPBIAS.
■ Powerdown features to conserve energy in batterypowered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
— Automatic microlow-power sleep mode during suspend.
■ Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation.
Features
■ Provides two fully compliant cable ports at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
■ Fully supports OHCI requirements.
■ Supports arbitrated short bus reset to improve utilization of the bus.
■ Supports ack-accelerated arbitration and fly-by concatenation.
■ Supports connection debounce.
■ Supports multispeed packet concatenation.
■ Supports PHY pinging and remote PHY access packets.
■ Fully supports suspend/resume.
■ Supports PHY-link interface initialization and reset.
■ Supports 1394a-2000 register set.
■ Supports LPS/link-on as a part of PHY-link interface.
■ Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus.
■ Fully interoperable with FireWire? implementation of IEEE 1394-1995.
■ Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V.
■ Separate cable bias and driver termination voltage supply for each port.
■ Meets Intel? Mobile Power Guideline 2000.
Other Features
■ 64-pin TQFP package.
■ Single 3.3 V supply operation.
■ Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s.
■ 25 MHz crystal oscillator and PLL provide transmit/ receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and link-layer controller clock at 50 MHz.
■ Node power-class information signaling for system power management.
■ Multiple separate package signals provided for analog and digital supplies and grounds.
產(chǎn)品屬性
- 型號(hào):
FW802
- 制造商:
AGERE
- 制造商全稱(chēng):
AGERE
- 功能描述:
Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
AGERE |
24+ |
QFP |
6430 |
原裝現(xiàn)貨/歡迎來(lái)電咨詢(xún) |
詢(xún)價(jià) | ||
AGERE |
24+ |
QFP-48 |
16800 |
絕對(duì)原裝進(jìn)口現(xiàn)貨,假一賠十,價(jià)格優(yōu)勢(shì)!? |
詢(xún)價(jià) | ||
AGERE |
24+ |
TQFP-64 |
1068 |
原裝現(xiàn)貨假一罰十 |
詢(xún)價(jià) | ||
AGERE |
20+ |
QFP |
500 |
樣品可出,優(yōu)勢(shì)庫(kù)存歡迎實(shí)單 |
詢(xún)價(jià) | ||
Intel |
23+ |
XX |
20000 |
原廠原裝正品現(xiàn)貨 |
詢(xún)價(jià) | ||
LUCENT |
22+ |
QFP |
9600 |
原裝現(xiàn)貨,優(yōu)勢(shì)供應(yīng),支持實(shí)單! |
詢(xún)價(jià) | ||
Intel |
21+ |
60-TFBGA |
1000 |
進(jìn)口原裝!長(zhǎng)期供應(yīng)!絕對(duì)優(yōu)勢(shì)價(jià)格(誠(chéng)信經(jīng)營(yíng) |
詢(xún)價(jià) | ||
INTEL |
BGAQFP |
6688 |
15 |
現(xiàn)貨庫(kù)存 |
詢(xún)價(jià) | ||
Intel |
23+ |
XX |
999999 |
原裝正品現(xiàn)貨量大可訂貨 |
詢(xún)價(jià) | ||
AGERE |
04+ |
QFP |
50 |
向鴻原裝正品/代理渠道/現(xiàn)貨優(yōu)勢(shì) |
詢(xún)價(jià) |