GENERAL DESCRIPTION

The AD5696 and AD5694, members of the nanoDAC+? family, are low power, quad, 16-/12-bit buffered voltage output DACs. The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1 FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.

FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1 of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1 of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

400 kHz I2C-compatible serial interface

4 I2C addresses available

Low glitch: 0.5 nV-sec

Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating

Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

?40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment

Programmable attenuators

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

EVAL-AD5696RSDZ屬于開發(fā)板，套件，編程器 > 評(píng)估板 - 數(shù)模轉(zhuǎn)換器（DAC）。亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的EVAL-AD5696RSDZ評(píng)估板 - 數(shù)模轉(zhuǎn)換器（DAC）該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗(yàn)證的設(shè)計(jì)環(huán)境中對(duì)用于將數(shù)字?jǐn)?shù)據(jù)轉(zhuǎn)換為模擬格式的器件進(jìn)行性能或特性評(píng)估。重點(diǎn)器件涵蓋范圍從以適合學(xué)生或愛好者使用的方式實(shí)現(xiàn)的適度功能器件，到適合電信基礎(chǔ)設(shè)施應(yīng)用的高級(jí)器件。