EPM7096中文資料阿爾特數(shù)據(jù)手冊PDF規(guī)格書
EPM7096規(guī)格書詳情
General Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
Features...
■ High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX? architecture
■ 5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
■ PCI-compliant devices available
■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50 in
each macrocell
■ Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
■ Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
– Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
■ Programming support
– Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
– The BitBlasterTM serial download cable, ByteBlasterMVTM
parallel port download cable, and MasterBlasterTM
serial/universal serial bus (USB) download cable program MAX
7000S devices
產(chǎn)品屬性
- 型號:
EPM7096
- 制造商:
ALTERA
- 制造商全稱:
Altera Corporation
- 功能描述:
Programmable Logic Device Family
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
ALTERA |
2016+ |
PLCC-84 |
8880 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
ALTERA |
2019+ |
PLCC |
6000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價 | ||
ALTERA |
20+ |
PLCC68 |
67500 |
原裝優(yōu)勢主營型號-可開原型號增稅票 |
詢價 | ||
ALTERA/阿爾特拉 |
23+ |
PLCC |
20000 |
原廠原裝正品現(xiàn)貨 |
詢價 | ||
LATT |
1948+ |
LDCC84 |
6852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價 | ||
ALT |
1997 |
77 |
原裝正品現(xiàn)貨庫存價優(yōu) |
詢價 | |||
ALTERA |
23+ |
NA |
3680 |
專業(yè)電子元器件供應(yīng)鏈正邁科技特價代理QQ1304306553 |
詢價 | ||
ALTERA |
17+ |
PLCC |
9600 |
只做全新進(jìn)口原裝,現(xiàn)貨庫存 |
詢價 | ||
ALTERA |
00+ |
PLCC84 |
3560 |
全新原裝進(jìn)口自己庫存優(yōu)勢 |
詢價 | ||
ALTERA |
97+ |
PLCC84P |
25 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
詢價 |