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EBE10EE8ACFA中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書
EBE10EE8ACFA規(guī)格書詳情
Features
? Double-data-rate architecture; two data transfers per clock cycle
? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
? DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
? Differential clock inputs (CK and /CK)
? DLL aligns DQ and DQS transitions with CK transitions
? Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
? Data mask (DM) for write data
? Posted /CAS by programmable additive latency for better command and data bus efficiency
? Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
? /DQS can be disabled for single-ended Data Strobe operation
產(chǎn)品屬性
- 型號：
EBE10EE8ACFA
- 制造商：
ELPIDA
- 制造商全稱：
Elpida Memory
- 功能描述：
1GB Unbuffered DDR2 SDRAM DIMM
