EBD21RD4ABNA-7B中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書

Description

The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TCP on the module board.

Features

? 184-pin socket type dual in line memory module (DIMM)

- PCB height: 30.48mm

- Lead pitch: 1.27mm

? 2.5V power supply

? Data rate: 266Mbps/200Mbps (max.)

? 2.5 V (SSTL_2 compatible) I/O

? Double Data Rate architecture; two data transfers per clock cycle

? Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

? Data inputs and outputs are synchronized with DQS

? 4 internal banks for concurrent operation (Component)

? DQS is edge aligned with data for READs; center

aligned with data for WRITEs

? Differential clock inputs (CK and /CK)

? LL aligns DQ and DQS transitions with CK transitions

? Commands entered on each positive CK edge; data

referenced to both edges of DQS

? Auto precharge option for each burst access

? Programmable burst length: 2, 4, 8

? Programmable /CAS latency (CL): 2, 2.5

? Refresh cycles: (8192 refresh cycles /64ms)

- 7.8μs maximum average periodic refresh interval

? 2 variations of refresh

- Auto refresh

- Self refresh

? 1 piece of PLL clock driver, 1 piece of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)