DSP56800ERM中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

56F8014 General Description

? Up to 32 MIPS at 32MHz core frequency

? DSP and MCU functionality in a unified, C-efficient architecture

? 16KB Program Flash

? 4KB Unified Data/Program RAM

? One 5-channel PWM module

? Two 4-channel 12-bit ADCs

? One Serial Communication Interface (SCI) with LIN slave functionality

? One Serial Peripheral Interface (SPI)

? One 16-bit Quad Timer

? One Inter-Integrated Circuit (I2C) Port

? Computer Operating Properly (COP)/Watchdog

? On-Chip Relaxation Oscillator

? Integrated Power-On Reset and Low-Voltage Interrupt Module

? JTAG/Enhanced On-Chip Emulation (OnCE?) for unobtrusive, real-time debugging

? Up to 26 GPIO lines

? 32-pin LQFP Package