DS21455N集成電路（IC）的電信規(guī)格書PDF中文資料

GENERAL DESCRIPTION

The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad MCM device. The DS21458, in a smaller package (17mm CSBGA) and featuring an improved controller interface, is software compatible with the older DS21Q55.

FEATURES

Four Independent Transceivers, Each Having the Following Features:

■ Complete T1 (DS1)/ISDN-PRI/J1 Transceiver Functionality

■ Complete E1 (CEPT) PCM-30/ISDNPRI Transceiver Functionality

■ Short- and Long-Haul Line Interface for Clock/Data Recovery and Waveshaping

■ CMI Coder/Decoder

■ Crystal-Less Jitter Attenuator

■ Fully Independent Transmit and Receive Functionality

■ Dual HDLC Controllers

■ On-Chip Programmable BERT Generator and Detector

■ Internal Software-Selectable Receiveand Transmit-Side Termination Resistors for 75?/100?/120? T1 and E1 Interfaces

■ Dual Two-Frame Elastic-Store Slip Buffers that can Connect to Asynchronous Backplanes Up to 16.384MHz

■ 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Network Clock

■ Programmable Output Clocks for Fractional T1, E1, H0, and H12 Applications

■ Interleaving PCM Bus Operation

■ 8-Bit Parallel Control Port, Multiplexed or Nonmultiplexed, Intel or Motorola

■ IEEE 1149.1 JTAG-Boundary Scan

■ 3.3V Supply with 5V Tolerant Inputs and Outputs

■ DS21455 Directly Replaces DS21Q55

■ Signaling System 7 (SS7) Support

■ RAI-CI, AIS-CI Support