DAC1005D750HW集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

Features and benefits

? Dual 10-bit resolution

? 750 Msps maximum update rate

? Selectable 4? or 8? interpolation filters

? Input data rate up to 185 Msps

? Very low noise cap-free integrated PLL

? 32-bit programmable NCO frequency

? Dual port or Interleaved data modes

? 1.8 V and 3.3 V power supplies

? LVDS compatible clock

? Two’s complement or binary offset

data format

? 1.8 V/3.3 V CMOS input data buffers

? IMD3: 74 dBc; fs = 737.28 Msps;

fo = 140 MHz

? ACPR: 64 dBc; 2-carrier WCDMA;

fs = 737.28 Msps; fo = 153.6 MHz

? Typical 1.2 W power dissipation at 4?

interpolation, PLL off and 740 Msps

? Power-down and Sleep modes

? Differential scalable output current from

1.6 mA to 22 mA

? On-chip 1.29 V reference

? External analog offset control

(10-bit auxiliary DACs)

? Internal digital offset control

? Inverse x / (sin x) function

? Fully compatible SPI port

? Industrial temperature range from

?40C to +85C