CY7C1351F-100BGI中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

? Can support up to 133-MHz bus operations with zero wait states

— Data is transferred on every clock

? Pin compatible and functionally equivalent to ZBT? devices

? Internally self-timed output buffer control to eliminate the need to use OE

? Registered inputs for flow-through operation

? Byte Write capability

? 128K x 36 common I/O architecture

? 2.5V / 3.3V I/O power supply

? Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

— 8.0 ns (for 100-MHz device)

— 11.0 ns (for 66-MHz device)

? Clock Enable (CEN) pin to suspend operation

? Synchronous self-timed writes

? Asynchronous Output Enable

? JEDEC-standard 100 TQFP and 119 BGA packages

? Burst Capability—linear or interleaved burst order

? Low standby power