首頁>CY7C1031-12JC>規(guī)格書詳情
CY7C1031-12JC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書
相關(guān)芯片規(guī)格書
更多CY7C1031-12JC規(guī)格書詳情
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.
Features
? Supports 66-MHz Pentium? microprocessor cache systems with zero wait states
? 64K by 18 common I/O
? Fast clock-to-output times
— 8.5 ns
? Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (7C1031)
? Two-bit wraparound counter supporting linear burst sequence (7C1032)
? Separate processor and controller address strobes
? Synchronous self-timed write
? Direct interface with the processor and external cache controller
? Asynchronous output enable
? I/Os capable of 3.3V operation
? JEDEC-standard pinout
? 52-pin PLCC packaging
產(chǎn)品屬性
- 型號(hào)：
CY7C1031-12JC
- 制造商：
Cypress Semiconductor
- 功能描述：
SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 12ns 52-Pin PLCC T/R
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
2023+ |
80000 |
一級(jí)代理/分銷渠道價(jià)格優(yōu)勢(shì) 十年芯程一路只做原裝正品 |
詢價(jià) | |||
ADI |
23+ |
DIP-16 |
6500 |
全新原裝假一賠十 |
詢價(jià) | ||
CYPRESS |
23+ |
PLCC52 |
143 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
CYPRESS |
0029+/0124+ |
PLCC52 |
133 |
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) | ||
CYPRESS |
2020+ |
PLCC |
80000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) | ||
CYP |
1997 |
44 |
原裝正品現(xiàn)貨庫存價(jià)優(yōu) |
詢價(jià) | |||
CYPRESS |
17+ |
PLCC |
9600 |
只做全新進(jìn)口原裝,現(xiàn)貨庫存 |
詢價(jià) | ||
CYPRESS |
21+ |
PLCC52 |
143 |
原裝現(xiàn)貨假一賠十 |
詢價(jià) | ||
CYP |
23+ |
PLCC52 |
9526 |
詢價(jià) | |||
CYPRESS |
24+ |
PLCC |
16800 |
絕對(duì)原裝進(jìn)口現(xiàn)貨,假一賠十,價(jià)格優(yōu)勢(shì)!? |
詢價(jià) |
