CSPT855集成電路（IC）的應(yīng)用特定時鐘/定時規(guī)格書PDF中文資料

FEATURES:

? PLL clock driver for DDR (Double Data Rate) synchronous

DRAM applications

? Spread spectrum clock compatible

? Operating frequency: 60MHz to 220MHz

? Low jitter (cycle-to-cycle): ±50ps

? Distributes one differential clock input to four differential clock

outputs

? Enters low power mode and 3-state outputs when input CLK

signal is less than 20MHz or PWRDWN is low

? Operates from a 2.5V supply

? Consumes <200μA quiescent current

? External feedback pins (FBIN, FBIN) are used to synchronize

outputs to input clocks

? Available in TSSOP package

DESCRIPTION:

The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer

that distributes one differential clock input pair(CLK, CLK ) to four differential

output pairs (Y [0:3],Y [0:3]) and one differential pair of feedback clock outputs

(FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and

frequency with CLK. When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode). The

device also enters this low-power mode when the input frequency falls below

a suggested detection frequency that is below 20MHz (typical 10MHz). An input

frequency detection circuit detects the low-frequency condition, and after

applying a >20MHz input signal, this detection circuit reactivates the PLL and

enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test

purposes. The CSPT855 is also able to track spread spectrum clocking for

reduced EMI.

Since the CSPT855 is based on PLL circuitry, it requires a stabilization time

to achieve phase-lock of the PLL. This stabilization time is required following

power up