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CSP2510D集成電路(IC)的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

CSP2510D
廠商型號

CSP2510D

參數(shù)屬性

CSP2510D 封裝/外殼為24-TSSOP(0.173",4.40mm 寬);包裝為管件;類別為集成電路(IC)的時鐘發(fā)生器PLL頻率合成器;產(chǎn)品描述:IC CLK DVR PLL ZDB 1:10 24TSSOP

功能描述

3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

封裝外殼

24-TSSOP(0.173",4.40mm 寬)

文件大小

251.47 Kbytes

頁面數(shù)量

10

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-3-1 23:00:00

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CSP2510D規(guī)格書詳情

FEATURES:

? Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

? Distributes one clock input to one bank of ten outputs

? Output enable bank control

? External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

? No external RC network required for PLL loop stability

? Operates at 3.3V VDD

? tpd Phase Error at 166MHz: < ±150ps

? Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz

? Spread Spectrum Compatible

? Operating frequency 50MHz to 175MHz

? Available in 24-Pin TSSOP package

DESCRIPTION:

The CSP2510D is a high performance, low-skew, low-jitter, phase-lock

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CSP2510D

operates at 3.3V.

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Output signal duty cycles are adjusted to 50 percent, independent of the duty

cycle at CLK. The outputs can be enabled or disabled via the control G input.

When the G input is high, the outputs switch in phase and frequency with

CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CSP2510D does not require

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSP2510D requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL

can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510D is specified for operation from 0°C to +85°C. This device

is also available (on special order) in Industrial temperature range (-40°C

to +85°C). See ordering information for details.

產(chǎn)品屬性

  • 產(chǎn)品編號:

    CSP2510DPG8

  • 制造商:

    Renesas Electronics America Inc

  • 類別:

    集成電路(IC) > 時鐘發(fā)生器,PLL,頻率合成器

  • 包裝:

    管件

  • 類型:

    驅(qū)動器,PLL,零延遲緩沖器

  • PLL:

    帶旁路

  • 輸入:

    時鐘

  • 輸出:

    時鐘

  • 比率 - 輸入:

    1:10

  • 差分 - 輸入:

    無/無

  • 頻率 - 最大值:

    175MHz

  • 分頻器/倍頻器:

    無/無

  • 電壓 - 供電:

    3V ~ 3.6V

  • 工作溫度:

    0°C ~ 85°C

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    24-TSSOP(0.173",4.40mm 寬)

  • 供應(yīng)商器件封裝:

    24-TSSOP

  • 描述:

    IC CLK DVR PLL ZDB 1

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
IDT
23+
NA/
2520
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票
詢價
IDT
2020+
TSSOP24
80000
只做自己庫存,全新原裝進口正品假一賠百,可開13%增
詢價
IDT
24+
TSSOP24
990000
明嘉萊只做原裝正品現(xiàn)貨
詢價
IDT
22+
24TSSOP
9000
原廠渠道,現(xiàn)貨配單
詢價
IDT
12+
TSSOP
1070
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
詢價
IDT
TSSOP
68900
原包原標簽100%進口原裝常備現(xiàn)貨!
詢價
IDT
22+
TSSOP
6852
只做原裝正品現(xiàn)貨!或訂貨假一賠十!
詢價
IDT
22+
TSSOP
38582
鄭重承諾只做原裝進口貨
詢價
IDT
17+
TSSOP-24
6200
100%原裝正品現(xiàn)貨
詢價
INTEGRATED DEVICE TECHNOLOGY
2022+
原廠原包裝
8600
全新原裝 支持表配單 中國著名電子元器件獨立分銷
詢價